Add device tree binding for the Renesas RZ/V2M Counter Match Timer (a.k.a TIM). Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> --- .../counter/renesas,rzv2m-tim-cnt.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/renesas,rzv2m-tim-cnt.yaml diff --git a/Documentation/devicetree/bindings/counter/renesas,rzv2m-tim-cnt.yaml b/Documentation/devicetree/bindings/counter/renesas,rzv2m-tim-cnt.yaml new file mode 100644 index 000000000000..963dffe1c957 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/renesas,rzv2m-tim-cnt.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/renesas,rzv2m-tim-cnt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M Compare Match Timer (TIM) + +maintainers: + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> + +description: | + The Compare Match Timer(TIM) on RZ/V2M like SoCs has an internal 32-bit + counter that can be used as an interval timer. This LSI has a total of 32 + channels of TIM from ch. 0 to ch. 31. It supports the following features + * Configured with a 32-bit counter operating at INCLOCK (2 MHz) + * The clock input from the count clock input pin can be divided by 2, 4, + 8, 16, 32, 64, 128, or 256, and one of these divided clocks can be + used as the count clock. + * The counter period can be set in the range of 1 to 4294967296 + (32-bit timer) using the selected divider clock as the count clock. + * Generates an interrupt request signal every cycle set in the TIM + counter. + * The counter operation and the bus interface are asynchronous and + can operate independently regardless of the size of the respective + clock cycles. + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-tim-cnt # RZ/V2M + - renesas,r9a09g055-tim-cnt # RZ/V2MA + - const: renesas,rzv2m-tim-cnt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: TIM clock + + clock-names: + items: + - const: apb + - const: tim + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tim8: tim@a4000400 { + compatible = "renesas,r9a09g011-tim-cnt", "renesas,rzv2m-tim-cnt"; + reg = <0xa4000400 0x80>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>, + <&cpg CPG_MOD R9A09G011_TIM8_CLK>; + clock-names = "apb", "tim"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_TIM_GPB_PRESETN>; + }; -- 2.25.1
