On Fri, Nov 25, 2022 at 12:51:34PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Fri, Nov 25, 2022 at 12:25 PM Conor Dooley
> <conor.dooley@xxxxxxxxxxxxx> wrote:
> >
> > On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote:
> > > On 25/11/2022 11:34, Lad, Prabhakar wrote:
> > > >>> +/* Device, Non-bufferable */
> > > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2)
> > > >>> +/* Device, bufferable */
> > > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2)
> > > >>> +/* Memory, Non-cacheable, Non-bufferable */
> > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2)
> > > >>> +/* Memory, Non-cacheable, Bufferable */
> > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2)
> > > >>
> > > >> What are all these? They don't look like flags, because 3 = 1 | 2...
> > > >> they don't look like constants, because we do not use shifts in
> > > >> constants. Are these some register values? I also do not see the header
> > > >> being used in the code, so why having a bindings header if it is not
> > > >> used (DTS is not usage...)?
> > > >>
> > > > These are register bit values for the MTYP[5:2] field. The DTS example
> > > > in the binding doc (above) uses these macros. I haven't included the
> > > > DTS/I patches with this patchset yet do think I should?
> > >
> > > Then why storing it as bindings? Bindings headers describe the interface
> > > implemented by drivers and used by DTS, but this is not implemented by
> > > drivers.
> >
> > IIUC, some of these properties are non-discoverable attributes of the
> > cache controller. I see two things that could be done here that are
> > "better" than #defining bits:
> > - add an RZ/Five specific compatible and use match data to set the
> > attributes which is only possible if the pma-regions are set on a
> > per SoC basis
> > - make pma-regions into a child node, in which andestech,non-cacheable
> > andestech,non-bufferable etc are properties of the child node
> >
> For now the only way to get DMA working without IOCP is to have
> AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF. But for future purposes I have
> introduced the other available flags.
>
> So maybe for now we could just have this flag
> andestech,mem-non-cacheable-bufferable in the binding doc.
>
> cache-controller@2010000 {
> reg = <0x13400000 0x100000>;
> compatible = "andestech,ax45mp-cache", "cache";
> interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
> cache-line-size = <64>;
> cache-level = <2>;
> cache-sets = <1024>;
> cache-size = <262144>;
> cache-unified;
> andestech,pma-region@0x58000000 {
> reg = <0x58000000 0x08000000>;
> andestech,mem-non-cacheable-bufferable;
Yah, that's about what I would expect - except splitting the properties
up. I think split up makes more sense from a property description point
of view, rather than needing some sort of
oneOf:
- non-cacheable-bufferable
- cacheable-non-bufferable
- non-cacheable-non-bufferable
> };
> andestech,pma-region@0xdeadbeef {
> reg = <0xdeadbeef 0x08000000>;
> andestech,mem-non-cacheable-bufferable;
> };
> ....
> };
