Hi Krzysztof, Thank you for the review. On Fri, Nov 25, 2022 at 8:16 AM Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > On 24/11/2022 18:22, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > describes the L2 cache block. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > --- > > RFC v3 -> v4 > > * Dropped l2 cache configuration parameters > > * s/larger/large > > * Added minItems/maxItems for andestech,pma-regions > > --- > > .../cache/andestech,ax45mp-cache.yaml | 93 +++++++++++++++++++ > > .../cache/andestech,ax45mp-cache.h | 38 ++++++++ > > 2 files changed, 131 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > create mode 100644 include/dt-bindings/cache/andestech,ax45mp-cache.h > > > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > new file mode 100644 > > index 000000000000..bf255b177d0a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > @@ -0,0 +1,93 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Andestech AX45MP L2 Cache Controller > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > + > > +description: > > + A level-2 cache (L2C) is used to improve the system performance by providing > > + a large amount of cache line entries and reasonable access delays. The L2C > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > + > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - andestech,ax45mp-cache > > + > > + required: > > + - compatible > > + > > +properties: > > + compatible: > > + items: > > + - const: andestech,ax45mp-cache > > + - const: cache > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + cache-line-size: > > + const: 64 > > + > > + cache-level: > > + const: 2 > > + > > + cache-sets: > > + const: 1024 > > + > > + cache-size: > > + enum: [131072, 262144, 524288, 1048576, 2097152] > > + > > + cache-unified: true > > + > > + next-level-cache: true > > + > > + andestech,pma-regions: > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > + minItems: 1 > > + maxItems: 16 > > + items: > > + minItems: 3 > > + maxItems: 3 > > Instead: > items: > items: > - description: Explain > - description: what is > - description: here > Ok, I will do that in the next version. - description: Memory region offset to be set up in the PMA - description: Size of the PMA region - description: Flags indicating how the region should be set up in the PMA. (ETYP[1:0] | MTYP[5:2]) use the macros defined in include/dt-bindings/cache/andestech,ax45mp-cache.h. > > + description: Optional array of memory regions to be set in the PMA. > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - cache-line-size > > + - cache-level > > + - cache-sets > > + - cache-size > > + - cache-unified > > + - interrupts > > + - reg > > Keep the same order as properties appear in the "properties:" > Agreed, will do. > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/cache/andestech,ax45mp-cache.h> > > + > > + cache-controller@2010000 { > > + reg = <0x13400000 0x100000>; > > + compatible = "andestech,ax45mp-cache", "cache"; > > + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; > > + cache-line-size = <64>; > > + cache-level = <2>; > > + cache-sets = <1024>; > > + cache-size = <262144>; > > + cache-unified; > > + andestech,pma-regions = <0x58000000 0x08000000 > > + (AX45MP_PMACFG_ETYP_NAPOT | AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>; > > + }; > > diff --git a/include/dt-bindings/cache/andestech,ax45mp-cache.h b/include/dt-bindings/cache/andestech,ax45mp-cache.h > > new file mode 100644 > > index 000000000000..aa1cad24075d > > --- /dev/null > > +++ b/include/dt-bindings/cache/andestech,ax45mp-cache.h > > @@ -0,0 +1,38 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > > +/* > > + * This header provides constants for Andes AX45MP PMA configuration > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#ifndef __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H > > +#define __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H > > + > > +/* OFF: PMA entry is disabled */ > > +#define AX45MP_PMACFG_ETYP_DISABLED 0 > > +/* Naturally aligned power of 2 region */ > > +#define AX45MP_PMACFG_ETYP_NAPOT 3 > > + > > +/* Device, Non-bufferable */ > > +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > > +/* Device, bufferable */ > > +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > > +/* Memory, Non-cacheable, Non-bufferable */ > > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > > +/* Memory, Non-cacheable, Bufferable */ > > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > > What are all these? They don't look like flags, because 3 = 1 | 2... > they don't look like constants, because we do not use shifts in > constants. Are these some register values? I also do not see the header > being used in the code, so why having a bindings header if it is not > used (DTS is not usage...)? > These are register bit values for the MTYP[5:2] field. The DTS example in the binding doc (above) uses these macros. I haven't included the DTS/I patches with this patchset yet do think I should? Cheers, Prabhakar
