Hi Serge, On Sun, Nov 13, 2022 at 10:12:58PM +0300, Serge Semin wrote: > Currently the DW PCIe Root Port and Endpoint CSR spaces are retrieved in > the separate parts of the DW PCIe core driver. It doesn't really make > sense since the both controller types have identical set of the core CSR > regions: DBI, DBI CS2 and iATU/eDMA. Thus we can simplify the DW PCIe Host > and EP initialization methods by moving the platform-specific registers > space getting and mapping into a common method. It gets to be even more > justified seeing the CSRs base address pointers are preserved in the > common DW PCIe descriptor. Note all the OF-based common DW PCIe settings > initialization will be moved to the new method too in order to have a > single function for all the generic platform properties handling in single > place. > > A nice side-effect of this change is that the pcie-designware-host.c and > pcie-designware-ep.c drivers are cleaned up from all the direct dw_pcie > storage modification, which makes the DW PCIe core, Root Port and Endpoint > modules more coherent. Thanks for these new generic interfaces in the DWC core! And thanks for the changes in this patch to take advantage of them in the pcie-designware drivers. Do you plan similar changes to other drivers to take advantage of these DWC-generic data and interfaces? If you add generic things to the DWC core but only take advantage of them in your driver, I don't think they are really usefully generic. Bjorn
