On 18/11/2022 17:50, Emil Renner Berthing wrote: > On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> wrote: >> >> From: Emil Renner Berthing <kernel@xxxxxxxx> >> >> Add bindings for the system clock and reset generator (SYSCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> >> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> >> --- >> .../clock/starfive,jh7110-syscrg.yaml | 80 +++++++++++++++++++ >> MAINTAINERS | 2 +- >> 2 files changed, 81 insertions(+), 1 deletion(-) >> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> new file mode 100644 >> index 000000000000..a8cafbc0afe2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> @@ -0,0 +1,80 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 System Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@xxxxxxxx> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-syscrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: RMII reference clock >> + - description: RGMII RX clock >> + - description: I2S TX bit clock >> + - description: I2S TX left/right clock >> + - description: I2S RX bit clock >> + - description: I2S RX left/right clock >> + - description: TDM >> + - description: mclk > > Maybe you could ask your colleagues for a better description of these clocks. And drop "clock" from previous descriptions. All these are clocks, so no need to repeat it. Best regards, Krzysztof
