On 16/11/2022 23:09, Rob Herring wrote: > On Tue, Nov 15, 2022 at 08:20:04PM +0530, Shubhrajyoti Datta wrote: >> The Clocking Wizard for Versal adaptive compute acceleration platforms >> generates multiple configurable number of clock outputs. >> Add device tree binding for Versal clocking wizard support. >> >> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> >> --- >> >> Changes in v2: >> rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in dt > > Why? Now you don't match the other clocking wizard. Yes, 'clk' is kind > of redundant, but making up different names for each version of h/w is > worse. > > What happened to using the same schema file so we aren't defining the > same property (xlnx,nr-outputs) twice? This might have been effect of my early comment, but then we discovered we have more of bindings for the same, thus my comment might not be applicable. Best regards, Krzysztof
