On Tue, Nov 15, 2022 at 08:20:04PM +0530, Shubhrajyoti Datta wrote: > The Clocking Wizard for Versal adaptive compute acceleration platforms > generates multiple configurable number of clock outputs. > Add device tree binding for Versal clocking wizard support. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> > --- > > Changes in v2: > rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in dt Why? Now you don't match the other clocking wizard. Yes, 'clk' is kind of redundant, but making up different names for each version of h/w is worse. What happened to using the same schema file so we aren't defining the same property (xlnx,nr-outputs) twice? > Update the compatible to reflect versal > > .../clock/xlnx,versal-clk-wizard.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml > new file mode 100644 > index 000000000000..aaba91a57713 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/xlnx,versal-clk-wizard.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> > + > +description: > + The clocking wizard is a soft ip clocking block of Xilinx Versal. The IP > + uses the input clock frequencies and generates the requested > + clock output. > + > +properties: > + compatible: > + const: xlnx,versal-clk-wizard > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + description: External input clocks to the given clock controller. > + items: > + - description: functional clock input > + - description: axi clock or the interface clock > + > + clock-names: > + items: > + - const: in1 > + - const: s_axi > + > + xlnx,nr-outputs: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 8 > + description: > + Number of outputs. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - clocks > + - clock-names > + - xlnx,nr-outputs > + > +additionalProperties: false > + > +examples: > + - | > + clock-generator@40040000 { > + compatible = "xlnx,versal-clk-wizard"; > + reg = <0x40040000 0x1000>; > + #clock-cells = <1>; > + clocks = <&clkc 15>, <&clkc 15>; > + clock-names = "in1", "s_axi"; > + xlnx,nr-outputs = <6>; > + }; > +... > -- > 2.17.1 > >
