Hi Prabhakar,
On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is
> identical to one found on the RZ/G2L SoC. No driver changes are
> required as generic compatible string "renesas,rzg2l-irqc" will be
> used as a fallback.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> ---
> Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five
> - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt
> domain) -> RISCV INTC
I think this difference is purely a software difference, and abstracted
in DTS through the interrupt hierarchy.
Does it have any impact on the bindings?
> - On the RZ/Five we have additional registers for IRQC block
Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus
warranting separate compatible values.
> - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC
Can you please elaborate? I may have missed something, but to me it
looks like that is exactly the same on RZ/G2UL and on RZ/Five.
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -26,6 +26,7 @@ properties:
> compatible:
> items:
> - enum:
> + - renesas,r9a07g043u-irqc # RZ/G2UL
> - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> - renesas,r9a07g054-irqc # RZ/V2L
> - const: renesas,rzg2l-irqc
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
