On 03/11/22 10:11, Matt Ranostay wrote: > From: Aswath Govindraju <a-govindraju@xxxxxx> > > x1 lane PCIe slot in the common processor board is enabled and connected to > J721S2 SOM. Add PCIe DT node in common processor board to reflect the > same. > > Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> > Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx> > Signed-off-by: Matt Ranostay <mranostay@xxxxxx> > --- > .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) Reviewed-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
