Matt, On 03/11/22 10:11 am, Matt Ranostay wrote: > Add dt node for the single instance of WIZ (SERDES wrapper) and > SERDES module shared by PCIe, eDP and USB. > > Cc: Vignesh Raghavendra <vigneshr@xxxxxx> > Cc: Nishanth Menon <nm@xxxxxx> > Signed-off-by: Matt Ranostay <mranostay@xxxxxx> > --- > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 53 ++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index 93b71d079b4f..6f9ccf52363e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -5,6 +5,16 @@ > * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include <dt-bindings/phy/phy-cadence.h> > +#include <dt-bindings/phy/phy-ti.h> > + > +/ { > + serdes_refclk: clock-cmnrefclk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + }; > +}; > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -38,6 +48,13 @@ usb_serdes_mux: mux-controller-0 { > #mux-control-cells = <1>; > mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ > }; > + > + serdes_ln_ctrl: mux-controller-80 { > + compatible = "mmio-mux"; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ > + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ > + }; > }; > > gic500: interrupt-controller@1800000 { > @@ -768,6 +785,42 @@ usb0: usb@6000000 { > }; > }; > > + serdes_wiz0: wiz@5060000 { > + compatible = "ti,am64-wiz-10g"; Should this be "ti,am64-wiz-10g" or "ti,j721e-wiz-10g" ? > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x5060000 0x0 0x5060000 0x10000>; > + > + assigned-clocks = <&k3_clks 365 3>; > + assigned-clock-parents = <&k3_clks 365 7>; > + > + serdes0: serdes@5060000 { > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x05060000 0x00010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz0 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 365 3>, > + <&k3_clks 365 3>, > + <&k3_clks 365 3>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + }; > + }; > + > main_mcan0: can@2701000 { > compatible = "bosch,m_can"; > reg = <0x00 0x02701000 0x00 0x200>, -- Regards, Ravi
