On 14/11/2022 16:04, Anup Patel wrote: > On Mon, Nov 14, 2022 at 5:52 PM Krzysztof Kozlowski >>>>> + riscv,slow-ipi: >>>>> + type: boolean >>>>> + description: >>>>> + The presence of this property implies that software interrupts (i.e. >>>>> + IPIs) using IMSIC software injected MSIs is slower compared to other >>>>> + software interrupt mechanisms (such as SBI IPI) on the underlying >>>>> + RISC-V platform. >>>> >>>> Is this a property of software or hardware? >>> >>> This is a property of hardware (or implementation) because IPIs >>> in IMSIC are software injected MSIs so if IMSIC is trap-n-emulated >>> by a hypervisor then all writes to MSI register will trap to hypervisor >>> in which case IPI injection via IMSIC is slow. >>> >>> The presence of "riscv,slow-ipi" DT property provides a hint to >>> driver that using IPIs through IMSIC is slow on this platform so >>> if there are other IPI mechanisms (such as SBI IPI calls) then >>> OS should prefer those mechanisms. >> >> If this is specific to implementation, why it is not included already in >> the compatible? >> >> The name is anyway too vague. What is "slow"? Describe real >> characteristics of hardware, e.g. trapped via hypervisor. > > Okay, how about renaming it to "riscv,trap-n-emulated" ? Sounds ok. > > Alternately, we can add "riscv,soft-imsics" as an implementation > specific compatible string which hypervisors can use to describe > trap-n-emulated IMSICs. This "riscv,soft-imsics" can also replace > "vendor,chip-imsics" dummy string ? soft-imsics would work only if it is a real device. My question was rather whether this is something configurable or fixed in given implementation. Best regards, Krzysztof
