On Sun, Nov 13, 2022 at 8:18 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > Hey Anup, > > On Fri, Nov 11, 2022 at 10:12:02AM +0530, Anup Patel wrote: > > dt-bindings: Add RISC-V incoming MSI controller bindings > > nit: it looks like the usual prefix here is "dt-bindings: > interrupt-controller". Okay, I will update. > > > We add DT bindings document for RISC-V incoming MSI controller (IMSIC) > > defined by the RISC-V advanced interrupt architecture (AIA) specification. > > > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > > --- > > .../interrupt-controller/riscv,imsic.yaml | 174 ++++++++++++++++++ > > 1 file changed, 174 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsic.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsic.yaml > > new file mode 100644 > > index 000000000000..05106eb1955e > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsic.yaml > > @@ -0,0 +1,174 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsic.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: RISC-V Incoming MSI Controller (IMSIC) > > + > > +maintainers: > > + - Anup Patel <anup@xxxxxxxxxxxxxx> > > + > > +description: > > Is this one of the situations where we want to have a | after > "description:" to preserve formatting? Okay, I will update. > > > + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming > > + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V > > + AIA specification can be found at https://github.com/riscv/riscv-aia. > > + > > + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file > > + for each privilege level (machine or supervisor). The configuration of > > + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO > > + space to receive MSIs from devices. Each IMSIC interrupt file supports a > > + fixed number of interrupt identities (to distinguish MSIs from devices) > > + which is same for given privilege level across CPUs (or HARTs). > > + > > + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform > > + follows a particular scheme defined by the RISC-V AIA specification. A IMSIC > > + group is a set of IMSIC interrupt files co-located in MMIO space and we can > > + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a > > + RISC-V platform. The MSI target address of a IMSIC interrupt file at given > > + privilege level (machine or supervisor) encodes group index, HART index, > > + and guest index (shown below). > > + > > + XLEN-1 >=24 12 0 > > + | | | | > > + ------------------------------------------------------------- > > + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > > + ------------------------------------------------------------- > > + > > + The device tree of a RISC-V platform will have one IMSIC device tree node > > + for each privilege level (machine or supervisor) which collectively describe > > + IMSIC interrupt files at that privilege level across CPUs (or HARTs). > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - vendor,chip-imsics > > Is it valid to have a dummy here? I did a bit of grepping & could not > see a single other yaml binding which used a placeholder like this - > other than the example schema itself. I assume you're trying to get > across the point that using the bare riscv,imsics is not okay and a > vendor should create a custom string for their implementation? Yes, this dummy is a placeholder to mandate two compatible strings. The dummy can eventually be replaced by some actual implementation compatible string. > > Also, the file name says "riscv,imsic", the description says "IMSIC" but > you've used "imsics" in the compatible. Is this a typo, or a plural? Yes, the file name should be consistent. I will update the file name. > > Thanks, > Conor. > > > + - const: riscv,imsics > > + > > + reg: > > + minItems: 1 > > + maxItems: 128 > > + description: > > + Base address of each IMSIC group. > > + > > + interrupt-controller: true > > + > > + "#interrupt-cells": > > + const: 0 > > + > > + msi-controller: true > > + > > + interrupts-extended: > > + minItems: 1 > > + maxItems: 32768 > > + description: > > + This property represents the set of CPUs (or HARTs) for which given > > + device tree node describes the IMSIC interrupt files. Each node pointed > > + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V > > + HART) as parent. > > + > > + riscv,num-ids: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 63 > > + maximum: 2047 > > + description: > > + Specifies how many interrupt identities are supported by IMSIC interrupt > > + file. > > + > > + riscv,num-guest-ids: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 63 > > + maximum: 2047 > > + description: > > + Specifies how many interrupt identities are supported by IMSIC guest > > + interrupt file. When not specified the number of interrupt identities > > + supported by IMSIC guest file is assumed to be same as specified by > > + the riscv,num-ids property. > > + > > + riscv,slow-ipi: > > + type: boolean > > + description: > > + The presence of this property implies that software interrupts (i.e. > > + IPIs) using IMSIC software injected MSIs is slower compared to other > > + software interrupt mechanisms (such as SBI IPI) on the underlying > > + RISC-V platform. > > + > > + riscv,guest-index-bits: > > + minimum: 0 > > + maximum: 7 > > + description: > > + Specifies number of guest index bits in the MSI target address. When > > + not specified it is assumed to be 0. > > + > > + riscv,hart-index-bits: > > + minimum: 0 > > + maximum: 15 > > + description: > > + Specifies number of HART index bits in the MSI target address. When > > + not specified it is estimated based on the interrupts-extended property. > > + > > + riscv,group-index-bits: > > + minimum: 0 > > + maximum: 7 > > + description: > > + Specifies number of group index bits in the MSI target address. When > > + not specified it is assumed to be 0. > > + > > + riscv,group-index-shift: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 24 > > + maximum: 55 > > + description: > > + Specifies the least significant bit of the group index bits in the > > + MSI target address. When not specified it is assumed to be 24. > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupt-controller > > + - msi-controller > > + - interrupts-extended > > + - riscv,num-ids > > + > > +examples: > > + - | > > + // Example 1 (Machine-level IMSIC files with just one group): > > + > > + imsic_mlevel: interrupt-controller@24000000 { > > + compatible = "vendor,chip-imsics", "riscv,imsics"; > > + interrupts-extended = <&cpu1_intc 11>, > > + <&cpu2_intc 11>, > > + <&cpu3_intc 11>, > > + <&cpu4_intc 11>; > > + reg = <0x28000000 0x4000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + msi-controller; > > + riscv,num-ids = <127>; > > + }; > > + > > + - | > > + // Example 2 (Supervisor-level IMSIC files with two groups): > > + > > + imsic_slevel: interrupt-controller@28000000 { > > + compatible = "vendor,chip-imsics", "riscv,imsics"; > > + interrupts-extended = <&cpu1_intc 9>, > > + <&cpu2_intc 9>, > > + <&cpu3_intc 9>, > > + <&cpu4_intc 9>; > > + reg = <0x28000000 0x2000>, /* Group0 IMSICs */ > > + <0x29000000 0x2000>; /* Group1 IMSICs */ > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + msi-controller; > > + riscv,num-ids = <127>; > > + riscv,group-index-bits = <1>; > > + riscv,group-index-shift = <24>; > > + }; > > +... > > -- > > 2.34.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@xxxxxxxxxxxxxxxxxxx > > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup
