Hi Boris, > -----Original Message----- > From: Borislav Petkov <bp@xxxxxxxxx> > Sent: Wednesday, November 9, 2022 12:09 AM > To: Potthuri, Sai Krishna <sai.krishna.potthuri@xxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@xxxxxxxxxx>; Michal Simek > <michal.simek@xxxxxxxxxx>; Mauro Carvalho Chehab > <mchehab@xxxxxxxxxx>; Tony Luck <tony.luck@xxxxxxxxx>; James Morse > <james.morse@xxxxxxx>; Robert Richter <rric@xxxxxxxxxx>; > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; linux-edac@xxxxxxxxxxxxxxx; > saikrishna12468@xxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx>; Datta, > Shubhrajyoti <shubhrajyoti.datta@xxxxxxx>; kernel test robot > <lkp@xxxxxxxxx> > Subject: Re: [PATCH v6 2/2] EDAC/zynqmp: Add EDAC support for Xilinx > ZynqMP OCM > > On Wed, Nov 02, 2022 at 12:36:55PM +0530, Sai Krishna Potthuri wrote: > > Add EDAC support for Xilinx ZynqMP OCM Controller, this driver > > So a while ago you said that this driver is for the on chip memory controller. > Is it possible for such a system to have another memory controller too for > which another EDAC driver gets loaded? > > Because the EDAC core - at least on x86 - assumes that a single driver runs on > the system and I don't think I've ever had the case where we need multiple > drivers. And in such case to audit it for concurrency issues. > > So I guess the question is, can a system have zynqmp_ocm_edac and say, > synopsys_edac or some other EDAC driver loaded at the same time? Yes, we have this scenario on Xilinx ZynqMP platform where we have both the drivers (zynqmp_ocm_edac - OCM Controller and synopsys_edac - DDR Memory Controller) probed at the same time. We tested this scenario on our platform (arm based), and we see both the controllers getting probed and tested by injecting errors. Probe log for both the controllers: xilinx-zcu102-20222:~$ dmesg | grep edac [ 1.642225] EDAC DEBUG: edac_mc_sysfs_init: device mc created [ 2.151781] EDAC DEBUG: edac_mc_alloc: allocating 2272 bytes for mci data (1 ranks, 1 csrows/channels) [ 2.151862] EDAC DEBUG: edac_mc_add_mc_with_groups: [ 2.151912] EDAC DEBUG: edac_create_sysfs_mci_device: device mc0 created [ 2.151945] EDAC DEBUG: edac_create_dimm_object: device rank0 created at location csrow 0 channel 0 [ 2.151979] EDAC DEBUG: edac_create_csrow_object: device csrow0 created [ 2.152020] EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (INTERRUPT) [ 2.161952] EDAC DEBUG: edac_device_register_sysfs_main_kobj: [ 2.162035] EDAC DEBUG: edac_device_add_device: [ 2.162039] EDAC DEBUG: find_edac_device_by_dev: [ 2.162043] EDAC DEBUG: edac_device_create_sysfs: idx=0 [ 2.162050] EDAC DEBUG: edac_device_create_instances: [ 2.162065] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT) Regards Sai Krishna
