This series adds support for the digital part of the DSI controller found in the A100 and D1 SoCs (plus T7, which is not supported by mainline Linux). There are two changes to the hardware integration: 1) the module clock routes through the TCON TOP, and 2) the separate I/O domain is removed. The actual register interface appears to be the same as before. The register definitions in the D1 BSP exactly match the A64 BSP. The BSP describes this as the "40nm" DSI controller variant. There is also a "28nm" variant with a different register interface; that one is found in a different subset of SoCs (V5 and A50). A100/D1 also come with an updated DPHY, described by the BSP as a "combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI share the same pins on Port D.) Since that is a different subsystem, I am sending that as a separate series. Changes in v2: - Add the variant check to the probe error path Samuel Holland (4): dt-bindings: display: sun6i-dsi: Fix clock conditional dt-bindings: display: sun6i-dsi: Add the A100 variant drm/sun4i: dsi: Add a variant structure drm/sun4i: dsi: Add the A100 variant .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 30 ++++++--- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 61 +++++++++++++------ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 7 +++ 3 files changed, 71 insertions(+), 27 deletions(-) -- 2.37.3
