The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.
Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index d29b48f23b89a..03592c8e63fed 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -262,6 +262,14 @@ ir: ir@1c22c00 {
status = "disabled";
};
+ lradc: lradc@1c23400 {
+ compatible = "allwinner,suniv-f1c100s-lradc",
+ "allwinner,sun8i-a83t-r-lradc";
+ reg = <0x01c23400 0x100>;
+ interrupts = <22>;
+ status = "disabled";
+ };
+
uart0: serial@1c25000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c25000 0x400>;
--
2.25.1
