On Mon, 31 Oct 2022 11:13:53 +0000, Andre Przywara wrote: > The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves > some resources from port 2's PHY and HCI IP. In particular the PMU clock > for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL > register of port 2. To allow each USB port to be controlled > independently of port 2, we need a handle to that particular PMU clock > in the *PHY* node, as the HCI and PHY part might be handled by separate > drivers. > > Add that clock to the requirements of the H616 PHY binding, so that a > PHY driver can apply the quirk in isolation, without requiring help from > port 2's HCI driver. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > --- > .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
