On 22-10-24, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@xxxxxxx>
>
> According to RM bit layout, BIT3 and BIT0 are reserved.
> 8 7 6 5 4 3 2 1 0
> PE HYS PUE ODE FSEL X DSE X
>
> Although function is not broken, we should not set reserved bit.
>
> Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
LGTM, feel free to add my:
Reviewed-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 9f1469db554d..b4c1ef2559f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -544,14 +544,14 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>
> pinctrl_pcie0: pcie0grp {
> fsl,pins = <
> - MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
> - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
> + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
> + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
> >;
> };
>
> pinctrl_pcie0_reg: pcie0reggrp {
> fsl,pins = <
> - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
> + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
> >;
> };
>
> --
> 2.37.1
>
>
>
