On 24/10/2022 05:42, Garmin.Chang wrote: > Add the new binding documentation for system clock > and functional clock on MediaTek MT8188. > > Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx> > --- > .../arm/mediatek/mediatek,mt8188-clock.yaml | 70 ++ > .../mediatek/mediatek,mt8188-sys-clock.yaml | 55 ++ > .../dt-bindings/clock/mediatek,mt8188-clk.h | 733 ++++++++++++++++++ > 3 files changed, 858 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml > create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml > new file mode 100644 > index 000000000000..49dc681e6601 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-clock.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Functional Clock Controller for MT8188 > + > +maintainers: > + - Garmin Chang <garmin.chang@xxxxxxxxxxxx> > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8188-adsp_audio26m No underscores in compatibles. > + - mediatek,mt8188-imp_iic_wrap_c > + - mediatek,mt8188-imp_iic_wrap_en > + - mediatek,mt8188-imp_iic_wrap_w > + - mediatek,mt8188-mfgcfg > + - mediatek,mt8188-vppsys0 > + - mediatek,mt8188-wpesys > + - mediatek,mt8188-wpesys_vpp0 > + - mediatek,mt8188-vppsys1 > + - mediatek,mt8188-imgsys > + - mediatek,mt8188-imgsys_wpe1 > + - mediatek,mt8188-imgsys_wpe2 > + - mediatek,mt8188-imgsys_wpe3 > + - mediatek,mt8188-imgsys1_dip_top > + - mediatek,mt8188-imgsys1_dip_nr > + - mediatek,mt8188-ipesys > + - mediatek,mt8188-camsys > + - mediatek,mt8188-camsys_rawa > + - mediatek,mt8188-camsys_yuva > + - mediatek,mt8188-camsys_rawb > + - mediatek,mt8188-camsys_yuvb > + - mediatek,mt8188-ccusys > + - mediatek,mt8188-vdecsys_soc > + - mediatek,mt8188-vdecsys > + - mediatek,mt8188-vencsys Blank line here > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + imp_iic_wrap_c: clock-controller@11283000 { Drop the label, not used, > + compatible = "mediatek,mt8188-imp_iic_wrap_c"; > + reg = <0x11283000 0x1000>; > + #clock-cells = <1>; > + }; > + > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml > new file mode 100644 > index 000000000000..35962b3746e1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys-clock.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek System Clock Controller for MT8188 > + > +maintainers: > + - Garmin Chang <garmin.chang@xxxxxxxxxxxx> > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The apmixedsys provides most of PLLs which generated from SoC 26m. > + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. > + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. > + The mcusys provides mux control to select the clock source in AP MCU. > + The device nodes also provide the system control capacity for configuration. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8188-topckgen > + - mediatek,mt8188-infracfg_ao Same comment. > + - mediatek,mt8188-apmixedsys > + - mediatek,mt8188-pericfg_ao > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + topckgen: syscon@10000000 { Drop label. > + compatible = "mediatek,mt8188-topckgen", "syscon"; > + reg = <0x10000000 0x1000>; > + #clock-cells = <1>; Best regards, Krzysztof
