Hi Geert, On Tue, Oct 25, 2022 at 5:13 PM Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > Hi Geert, > > Thank you for the review. > > On Tue, Oct 25, 2022 at 1:37 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > > > Hi Prabhakar, > > > > On Mon, Oct 17, 2022 at 11:12 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi > > > can be shared with RZ/Five (RISC-V SoC). > > > > > > Below are the changes due to which SoC specific parts are moved to > > > r9a07g043u.dtsi: > > > - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) > > > - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC > > > - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing > > > for SYSC block on RZ/Five > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Thanks for your patch! > > > > This assumes the operating points tables are the same for both variants? > > I guess that's OK. > > > Ive asked the HW team to confirm this. For the v2 I'll keep it as is > and later move it if required. > Ive confirmed with the HW team the OPP table is the same for both the variants. Cheers, Prabhakar
