Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Signed-off-by: Amjad Ouled-Ameur <aouledameur@xxxxxxxxxxxx> --- Changes in v3: - Fixed documentation by removing pinctrl states as they are not mandatory. - Link to v2: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@xxxxxxxxxxxx --- Amjad Ouled-Ameur (2): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle .../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 ++++++++++++++-------- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++++- 3 files changed, 94 insertions(+), 26 deletions(-) --- base-commit: aae703b02f92bde9264366c545e87cec451de471 change-id: 20221004-up-aml-fix-spi-c2bb7e78e603 Best regards, -- Amjad Ouled-Ameur <aouledameur@xxxxxxxxxxxx>
