With reference to FSD SoC HW UM, there are some deviations in the
drive strength macros names and macro values. Also the IPs are not
using the default drive strength values as recommended by HW UM.
FSD SoC pinctrl has following four levels of drive-strength and their
corresponding values:
Level-1 <-> 0
Level-2 <-> 1
Level-4 <-> 2
Level-6 <-> 3
The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support")
used drive strength macros defined for Exynos4 SoC family. For some IPs
the macros values of Exynos4 matched and worked well, but Exynos4 SoC
family drive-strength (names and values) is not exactly matching with
FSD SoC.
The intention of this patch series is to:
1. Fix the drive strength macros to reflect actual names and values given
in FSD HW UM.
2. Ensure that the existing peripherals in device tree file is using
default drive strength values recommended in FSD HW UM.
Padmanabhan Rajanbabu (4):
arm64: dts: fix drive strength macros as per FSD HW UM
arm64: dts: fix HSI2C drive strength values as per FSD HW UM
arm64: dts: fix UART drive strength values as per FSD HW UM
arm64: dts: fix SPI drive strength values as per FSD HW UM
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++-----------
arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++--
2 files changed, 20 insertions(+), 20 deletions(-)
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2.17.1
