From: Alexander Bahle <bahle@xxxxxxxxxxxxxxx> Add DT bindings for the PCIe PHY latencies in host and endpoint mode. Setting these improves the PTM timestamp accuracy. The values are taken from the Link below. Signed-off-by: Alexander Bahle <bahle@xxxxxxxxxxxxxxx> Signed-off-by: Dominic Rath <rath@xxxxxxxxxxxxxxx> Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/998749/am6442-details-regarding-ptm-implementation --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d6aa23681bbe..032abb343c36 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -855,6 +855,8 @@ pcie0_rc: pcie@f102000 { ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + cdns,tx-phy-latency-ps = <138800 69400>; + cdns,rx-phy-latency-ps = <185200 92600>; }; pcie0_ep: pcie-ep@f102000 { @@ -873,6 +875,8 @@ pcie0_ep: pcie-ep@f102000 { clocks = <&k3_clks 114 0>; clock-names = "fck"; max-functions = /bits/ 8 <1>; + cdns,tx-phy-latency-ps = <138800 69400>; + cdns,rx-phy-latency-ps = <185200 92600>; }; epwm0: pwm@23000000 { -- 2.36.0
