From: Emil Renner Berthing <kernel@xxxxxxxx> Add bindings for the system clock generator on the JH7110 RISC-V SoC by StarFive Technology Ltd. Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxxxxxxxx> --- .../clock/starfive,jh7110-clkgen-sys.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml new file mode 100644 index 000000000000..290b730145ab --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System Clock Generator + +maintainers: + - Emil Renner Berthing <kernel@xxxxxxxx> + - Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxxxxxxxx> + +properties: + compatible: + const: starfive,jh7110-clkgen-sys + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: RMII reference clock + - description: RGMII RX clock + - description: I2S TX bit clock + - description: I2S TX left/right clock + - description: I2S RX bit clock + - description: I2S RX left/right clock + - description: TDM + - description: mclk + + clock-names: + items: + - const: osc + - const: gmac1_rmii_refin + - const: gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices. + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscrg_clk: clock-controller@13020000 { + compatible = "starfive,jh7110-clkgen-sys"; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + }; -- 2.17.1
