On 23.9.2022 21:02, Pali Rohár wrote:
On Friday 23 September 2022 14:12:24 Andrew Lunn wrote:
> > > + if (of_machine_is_compatible("dlink,dns323a1")) {
> > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
> >
> > I spotted this in dns323-setup.c as well. Do you have any idea what it
> > does?
> >
>
> No idea. I have tried to replicate what was in dns323-setup.c as exactly as
> possible.
> I can try to leave it out and see if anything changes.
It is best to keep what we don't understand. It will be there for a
reason.
Andrew
Hello! I tried to index all publicly available Marvell SoC
documentations into kernel documentation subfolder:
https://docs.kernel.org/arm/marvell.html
For Orion there is linked Datasheet and User Manual, so you could try
to
find in those documents that mentioned register and check what it is
doing.
MPP_DEV_CTRL refers to register at address 0x10008. According to the
88F5152 user manual it's
'Device Multiplex Control Register' Offset: 0x10008.
Bits Field Type/InitVal Description
[31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'.
DEV_D[31:16] receives no hits in the documentation, only to DEV_D[15:0]
are referred.
Maybe 88F5151 is different, hard to say.
