Dear Krzysztof, Thanks for your comment. On Wed, 2022-09-21 at 10:24 +0200, Krzysztof Kozlowski wrote: > On 21/09/2022 09:07, Jianguo Zhang wrote: > > Add clk_csr property for snps,dwmac > > > > Signed-off-by: Jianguo Zhang <jianguo.zhang@xxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > index 491597c02edf..8cff30a8125d 100644 > > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > @@ -288,6 +288,11 @@ properties: > > is supported. For example, this is used in case of SGMII and > > MAC2MAC connection. > > > > + clk_csr: > > No underscores in node names. Missing vendor prefix. > We will remane the property name 'clk_csr' as 'snps,clk-csr' and another driver patch is needed to align the name used in driver with the new name. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: > > + Frequency division factor for MDC clock. > > Can't common clock framework do the job? What is the MDC clock? > MDC clock is used for ethernet MAC accessing PHY register by MDIO bus. There is frequency divider designed in ethernet internal HW to ensure that ethernet can get correct frequency of MDC colck and the vlaue of frequency divider can be got from DTS. > Best regards, > Krzysztof BRS Jianguo
