On Sat, 10 Sep 2022 22:42:32 +0300, Serge Semin wrote:
> The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC:
> the CSRs layout is absolutely different and it doesn't support IRQs unlike
> DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there
> is no any reason to have these controllers described in the same bindings.
> Let's split the DT-schema up.
>
> Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW
> uMCTL2 DDR controller only, we need to accordingly fix the device
> descriptions.
>
> [...]
Applied, thanks!
[14/19] dt-bindings: memory: snps: Detach Zynq DDRC controller support
https://git.kernel.org/krzk/linux-mem-ctrl/c/845081313632b6a27dff576cf102b4aecb4654cf
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
