Re: [PATCH 2/2] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

[Dinh Nguyen <dinguyen@xxxxxxxxxx>]

Hi Ulf,

Thanks for the review!

On 9/20/22 07:17, Ulf Hansson wrote:
> On Mon, 19 Sept 2022 at 20:13, Dinh Nguyen <dinguyen@xxxxxxxxxx> wrote:
> > The clock-phase settings for the SDMMC controller in the SoCFPGA
> > Strarix10/Agilex/N5X platforms reside in a register in the System
> > Manager. Add a method to access that register through the syscon
> > interface.
> >
> > Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> > ---
> >   drivers/mmc/host/dw_mmc-pltfm.c | 68 ++++++++++++++++++++++++++++++++-
> >   1 file changed, 67 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
> > index 9901208be797..9e3237c18a9d 100644
> > --- a/drivers/mmc/host/dw_mmc-pltfm.c
> > +++ b/drivers/mmc/host/dw_mmc-pltfm.c
> > @@ -17,10 +17,15 @@
> >   #include <linux/mmc/host.h>
> >   #include <linux/mmc/mmc.h>
> >   #include <linux/of.h>
> > +#include <linux/mfd/altera-sysmgr.h>
> > +#include <linux/regmap.h>
> >
> >   #include "dw_mmc.h"
> >   #include "dw_mmc-pltfm.h"
> >
> > +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> > +       ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
> > +
> >   int dw_mci_pltfm_register(struct platform_device *pdev,
> >                            const struct dw_mci_drv_data *drv_data)
> >   {
> > @@ -62,9 +67,70 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
> >   };
> >   EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
> >
> > +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> > +{
> > +       struct device_node *np = host->dev->of_node;
> > +       struct regmap *sys_mgr_base_addr;
> > +       u32 clk_phase[2] = {0}, reg_offset;
> > +       int i, rc, hs_timing;
> > +
> > +       rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
>
> This needs to be documented through updated DT bindings.

Ok, but it looks like clk-phase-sd-hs is already documented in 
Documentation/devicetree/bindings/mmc/mmc-controller.yaml

Should I create a specific documentation just for
"altr,socfpga-dw-mshc" and document "clk-phase-sd-hs"?

> > +       if (rc) {
> > +               sys_mgr_base_addr =
> > +                       altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
>
> DT bindings?

"altr,sysmgr-syscon" has already been documented in
Documentation/devicetree/bindings/net/socfpga-dwmac.txt

> > +               if (IS_ERR(sys_mgr_base_addr)) {
> > +                       pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> > +                       return 1;
> > +               }
> > +       } else
> > +               return 1;
> > +
> > +       of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
>
> DT bindings?

Same...

> > +
> > +       for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
> > +               switch (clk_phase[i]) {
> > +               case 0:
> > +                       clk_phase[i] = 0;
> > +                       break;
> > +               case 45:
> > +                       clk_phase[i] = 1;
> > +                       break;
> > +               case 90:
> > +                       clk_phase[i] = 2;
> > +                       break;
> > +               case 135:
> > +                       clk_phase[i] = 3;
> > +                       break;
> > +               case 180:
> > +                       clk_phase[i] = 4;
> > +                       break;
> > +               case 225:
> > +                       clk_phase[i] = 5;
> > +                       break;
> > +               case 270:
> > +                       clk_phase[i] = 6;
> > +                       break;
> > +               case 315:
> > +                       clk_phase[i] = 7;
> > +                       break;
> > +               default:
> > +                       clk_phase[i] = 0;
> > +                       break;
> > +               }
> > +       }
>
> In my opinion, it looks like converting to use
> mmc_of_parse_clk_phase() should be able to avoid some of the open
> coding above.
>
> If you need some inspiration of how to implement this, you may have a
> look at drivers/mmc/host/sdhci-of-aspeed.c

Got it.

> > +       hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> > +       regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct dw_mci_drv_data socfpga_drv_data = {
> > +       .init           = dw_mci_socfpga_priv_init,
> > +};
> > +
> >   static const struct of_device_id dw_mci_pltfm_match[] = {
> >          { .compatible = "snps,dw-mshc", },
> > -       { .compatible = "altr,socfpga-dw-mshc", },
> > +       { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, },
> >          { .compatible = "img,pistachio-dw-mshc", },
> >          {},
> >   };
> > --
> > 2.25.1
>
> Kind regards
> Uffe

Dinh