Hi Chris,
Thanks for my comments into account!
On 9/19/22 18:46, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@xxxxxxxxxxx>
>
> This adds the DSI controller nodes and DSI-DPHY controller nodes to the
> rk356x device tree.
>
> Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx>
Acked-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx>
Best regards,
Michael
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 80 ++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 319981c3e9f7..0473d7ee2668 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -699,6 +699,62 @@ vop_mmu: iommu@fe043e00 {
> status = "disabled";
> };
>
> + dsi0: dsi@fe060000 {
> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
> + reg = <0x00 0xfe060000 0x00 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "hclk";
> + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
> + phy-names = "dphy";
> + phys = <&dsi_dphy0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_DSITX_0>;
> + rockchip,grf = <&grf>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi0_in: port@0 {
> + reg = <0>;
> + };
> +
> + dsi0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dsi1: dsi@fe070000 {
> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
> + reg = <0x0 0xfe070000 0x0 0x10000>;
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "hclk";
> + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
> + phy-names = "dphy";
> + phys = <&dsi_dphy1>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_DSITX_1>;
> + rockchip,grf = <&grf>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi1_in: port@0 {
> + reg = <0>;
> + };
> +
> + dsi1_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> hdmi: hdmi@fe0a0000 {
> compatible = "rockchip,rk3568-dw-hdmi";
> reg = <0x0 0xfe0a0000 0x0 0x20000>;
> @@ -1594,6 +1650,30 @@ combphy2: phy@fe840000 {
> status = "disabled";
> };
>
> + dsi_dphy0: mipi-dphy@fe850000 {
> + compatible = "rockchip,rk3568-dsi-dphy";
> + reg = <0x0 0xfe850000 0x0 0x10000>;
> + clock-names = "ref", "pclk";
> + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
> + #phy-cells = <0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_MIPIDSIPHY0>;
> + status = "disabled";
> + };
> +
> + dsi_dphy1: mipi-dphy@fe860000 {
> + compatible = "rockchip,rk3568-dsi-dphy";
> + reg = <0x0 0xfe860000 0x0 0x10000>;
> + clock-names = "ref", "pclk";
> + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
> + #phy-cells = <0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_MIPIDSIPHY1>;
> + status = "disabled";
> + };
> +
> usb2phy0: usb2phy@fe8a0000 {
> compatible = "rockchip,rk3568-usb2phy";
> reg = <0x0 0xfe8a0000 0x0 0x10000>;
