Hello Krzysztof, On 19/09/22 15:45, Krzysztof Kozlowski wrote: > On 14/09/2022 11:39, Siddharth Vadapalli wrote: >> TI's J721e SoC supports additional PHY modes like QSGMII and SGMII >> that are not supported on earlier SoCs. Add a compatible for it. >> >> Extend ti,qsgmii-main-ports property to support selection of upto >> two main ports at once across the two QSGMII interfaces. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> >> --- >> .../bindings/phy/ti,phy-gmii-sel.yaml | 52 ++++++++++++++++--- >> 1 file changed, 46 insertions(+), 6 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> index da7cac537e15..1e19efab018b 100644 >> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> @@ -54,6 +54,7 @@ properties: >> - ti,dm814-phy-gmii-sel >> - ti,am654-phy-gmii-sel >> - ti,j7200-cpsw5g-phy-gmii-sel >> + - ti,j721e-cpsw9g-phy-gmii-sel >> >> reg: >> maxItems: 1 >> @@ -65,12 +66,19 @@ properties: >> description: | >> Required only for QSGMII mode. Array to select the port for >> QSGMII main mode. Rest of the ports are selected as QSGMII_SUB >> - ports automatically. Any one of the 4 CPSW5G ports can act as the >> - main port with the rest of them being the QSGMII_SUB ports. >> - maxItems: 1 >> - items: >> - minimum: 1 >> - maximum: 4 > > minItems: 1 > maxItems: 2 > items: > minimum: 1 > maximum: 8 Thank you for reviewing the patch. I assume that you want me to mention the values for "minItems", "maxItems", "minimum" and "maximum" here and modify them later based on the compatible where applicable. I will do so in the v2 series. > >> + ports automatically. For J7200 CPSW5G with the compatible: >> + ti,j7200-cpsw5g-phy-gmii-sel, ti,qsgmii-main-ports is an >> + array of only one element, which is the port number ranging from >> + 1 to 4. For J721e CPSW9G with the compatible: >> + ti,j721e-cpsw9g-phy-gmii-sel, ti,qsgmii-main-ports is an array >> + of two elements, which corresponds to two potential QSGMII main >> + ports. The first element and second element of the array can both >> + range from 1 to 8 each, corresponding to two QSGMII main ports. >> + For J721e CPSW9G, to configure port 2 as the first QSGMII main >> + port and port 7 as the second QSGMII main port, we specify: >> + ti,qsgmii-main-ports = <2>, <7>; >> + If only one QSGMII main port is desired, mention the same main >> + port twice. >> >> allOf: >> - if: >> @@ -81,12 +89,43 @@ allOf: >> - ti,dra7xx-phy-gmii-sel >> - ti,dm814-phy-gmii-sel >> - ti,am654-phy-gmii-sel >> + - ti,j7200-cpsw5g-phy-gmii-sel >> + - ti,j721e-cpsw9g-phy-gmii-sel >> then: >> properties: >> '#phy-cells': >> const: 1 >> description: CPSW port number (starting from 1) >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - ti,j7200-cpsw5g-phy-gmii-sel >> + then: >> + properties: >> + ti,qsgmii-main-ports: >> + maxItems: 1 >> + items: >> + minimum: 1 >> + maximum: 4 >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - ti,j721e-cpsw9g-phy-gmii-sel >> + then: >> + properties: >> + ti,qsgmii-main-ports: >> + minItems: 2 >> + maxItems: 2 >> + items: >> + minimum: 1 >> + maximum: 8 >> + >> - if: >> not: >> properties: >> @@ -94,6 +133,7 @@ allOf: >> contains: >> enum: >> - ti,j7200-cpsw5g-phy-gmii-sel >> + - ti,j721e-cpsw9g-phy-gmii-sel >> then: >> properties: >> ti,qsgmii-main-ports: false > > This is interesting here... Did you test the bindings with your DTS? Yes, I tried it out with different compatibles in the DTS file for the node, making sure that the property "ti,qsgmii-main-ports" is allowed only for the "ti,j7200-cpsw5g-phy-gmii-sel" and the "ti,j721e-cpsw9g-phy-gmii-sel" compatibles. Additionally, I also tested that the "minItems", "maxItems", "minimum" and "maximum" checks apply. All of the rules within the "allOf", are enforced one after the other in sequence, based on my testing. Please let me know in case of any suggestions to implement it in a better way. Regards, Siddharth.
