On 15/09/2022 00:12, Matej Vasilevski wrote: > Add second clock phandle to specify the timestamping clock. > > Signed-off-by: Matej Vasilevski <matej.vasilevski@xxxxxxxxx> > --- > .../bindings/net/can/ctu,ctucanfd.yaml | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > Thank you for your patch. There is something to discuss/improve. > diff --git a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > index 4635cb96fc64..432f0e3ed828 100644 > --- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > +++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml > @@ -44,9 +44,19 @@ properties: > > clocks: > description: | > - phandle of reference clock (100 MHz is appropriate > - for FPGA implementation on Zynq-7000 system). > - maxItems: 1 > + Phandle of reference clock (100 MHz is appropriate for FPGA > + implementation on Zynq-7000 system). Optionally add a phandle to > + the timestamping clock connected to timestamping counter, if used. > + minItems: 1 > + items: > + - description: core clock > + - description: timestamping clock > + > + clock-names: > + minItems: 1 > + items: > + - const: core-clk > + - const: ts-clk Skip the -clk suffixes, so just "core" and "ts". Best regards, Krzysztof
