From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> Add the big-endian property for LS1043A PCIe nodes for accessing PEX_LUT and PF register block. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> Signed-off-by: Li Yang <leoyang.li@xxxxxxx> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e1c5d685a9e3..3cf6722e7555 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -902,6 +902,7 @@ pcie1: pcie@3400000 { <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; fsl,pcie-scfg = <&scfg 0>; + big-endian; status = "disabled"; }; @@ -929,6 +930,7 @@ pcie2: pcie@3500000 { <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; fsl,pcie-scfg = <&scfg 1>; + big-endian; status = "disabled"; }; @@ -956,6 +958,7 @@ pcie3: pcie@3600000 { <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; fsl,pcie-scfg = <&scfg 2>; + big-endian; status = "disabled"; }; -- 2.37.1