On 11/09/2022 23:20, Johan Jonker wrote: > Convert rockchip,rk3128-cru.txt to YAML. > > Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx> Thank you for your patch. There is something to discuss/improve. > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml > new file mode 100644 > index 000000000..03e5d7f0e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0 Can't it be Dual licensed? > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU) > + > +maintainers: > + - Elaine Zhang <zhangqing@xxxxxxxxxxxxxx> > + - Heiko Stuebner <heiko@xxxxxxxxx> > + > +description: | > + The RK3126/RK3128 clock controller generates and supplies clock to various > + controllers within the SoC and also implements a reset controller for SoC > + peripherals. > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All available clocks are defined as > + preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be > + used in device tree sources. Similar macros exist for the reset sources in > + these files. > + There are several clocks that are generated outside the SoC. It is expected > + that they are defined using standard clock bindings with following > + clock-output-names: > + - "xin24m" - crystal input - required > + - "ext_i2s" - external I2S clock - optional > + - "gmac_clkin" - external GMAC clock - optional > + > +properties: > + compatible: > + enum: > + - rockchip,rk3126-cru > + - rockchip,rk3128-cru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: xin24m More clocks were mentioned in old binding. > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon managing the "general register files" (GRF), > + if missing pll rates are not changeable, due to the missing pll > + lock status. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + cru: clock-controller@20000000 { > + compatible = "rockchip,rk3128-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; Best regards, Krzysztof