Add support for USB DR on USB1 interface. Host/Device detection is done using the usb-role-switch connector. Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> --- Changes in v3: * Moved pinctrl to USB glue layer node * Ordered nodes alphabetically Changes in v2: * Split from previous series * For now enable USB OTG only .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index d8ca52976170..88579e8ac93b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -139,6 +139,13 @@ reg_vcc_3v3: regulator-3v3 { regulator-max-microvolt = <3300000>; }; + reg_vcc_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -445,6 +452,38 @@ &uart4 { status = "okay"; }; +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_vcc_5v0>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X29"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -666,6 +705,15 @@ pinctrl_uart4: uart4grp { <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; }; + pinctrl_usb0: usb0grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, + <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; + }; + + pinctrl_usbcon0: usb0congrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, -- 2.25.1