On Tue, 30 Aug 2022 13:51:33 +0100, Ben Dooks wrote: > With newer cores such as the p550, the SiFive composable cache can be > a level 3 cache. Update the cache level to be one of 2 or 3. > > Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
