On Mon, Aug 29, 2022 at 06:49:06PM -0700, Stephen Boyd wrote: > Quoting Daniel Mack (2022-08-26 02:11:22) > > The driver currently does 256 iterations of reads from the DEVICE_CTRL > > register to wait for the PLL_LOCK bit to clear, and sleeps one > > microsecond after each attempt. > > > > This isn't ideal because > > > > a) the total time this allows for the device to settle depends on the I2C > > bus speed, and > > b) the device might need more time, depending on the application. > > > > This patch allows users to configure this timeout through a new device-tree > > property "cirrus,pll-lock-timeout-ms". > > It's a timeout, so why not just increase the timeout regardless of > everything else? Or can we parse the bus speed (100kHz or 400kHz) > instead of adding a new property? My thought too. Usually PLLs have a spec for max/typ lock times. Given it's a should never happen type of thing, it doesn't seem like we need a super precise time. Rob
