Quoting Daniel Mack (2022-08-26 02:11:22) > The driver currently does 256 iterations of reads from the DEVICE_CTRL > register to wait for the PLL_LOCK bit to clear, and sleeps one > microsecond after each attempt. > > This isn't ideal because > > a) the total time this allows for the device to settle depends on the I2C > bus speed, and > b) the device might need more time, depending on the application. > > This patch allows users to configure this timeout through a new device-tree > property "cirrus,pll-lock-timeout-ms". It's a timeout, so why not just increase the timeout regardless of everything else? Or can we parse the bus speed (100kHz or 400kHz) instead of adding a new property? > > In order to not break existing applications, a default value of 100 ms is > assumed: For each read cycle, 8 bits are sent for the register address, and > 8 bits are read with the values. 16 bits take about 160 us on a 100 kHz bus > and 40 us on a 400 kHz bus. Hence 256 iterations would take a maximum of > around 44 ms. Round up and double that value to be on the safe side. >
