On 30/08/2022 14:49, Conor.Dooley@xxxxxxxxxxxxx wrote:
On 30/08/2022 13:58, Ben Dooks wrote:
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On 30/08/2022 13:56, Conor.Dooley@xxxxxxxxxxxxx wrote:
On 30/08/2022 13:51, Ben Dooks wrote:
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With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.
Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxx>
---
Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
const: 64
cache-level:
- const: 2
+ enum: [2, 3]
Do we want to enforce the cache level like we currently do for
interrupts and cache-sets?
Not sure on that, for the P550 cores the ccache is going to be level3
and my colleague has said it does confuse some tooling if the level is
not set correctly.
What I meant was:
Currently we enforce the correct cache-sets & interrupts based on the
compatible string. Adding enum: [2, 3] relaxes the enforcement of the
cache-level for existing compatibles and does not prevent someone from
setting an incorrect cache level for p550 cores.
I think that on top of adding the enum, we should add some enforcement
so that the cache is not incorrectly configured for both existing l2
caches and for the new l3 versions.
Ok, we can add some enforcement once we add the new bindings, but I'm
not ready for that today and I'd rather get the current queue sorted
out first before we come in with newer silicon which hasn't hit the
market uet.
@Zong, could you please incorporate Ben's patches into your V2? it
would make it a lot easier to review what's going on here. It may
also make sense to add the compatible for the p550 cache while we are
at it...
FYI, there is also this patch here outstanding against the l2:
https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@xxxxxxxxxxx/
I intend taking this into 6.0-rc5 or so as a fix, so if you could
rebase the series on that so it is not lost in the dt-binding rename
that would be great.
Do we need someone to take charge of this series?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
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