On 30/08/2022 13:56, Conor.Dooley@xxxxxxxxxxxxx wrote:
On 30/08/2022 13:51, Ben Dooks wrote:EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe With newer cores such as the p550, the SiFive composable cache can be a level 3 cache. Update the cache level to be one of 2 or 3. Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxx> --- Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml index 1a64a5384e36..6190deb65455 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -45,7 +45,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3]Do we want to enforce the cache level like we currently do for interrupts and cache-sets?
Not sure on that, for the P550 cores the ccache is going to be level3 and my colleague has said it does confuse some tooling if the level is not set correctly. -- Ben
