Daire and I are the platform maintainers for Microchip's RISC-V FPGAs. Update the maintainers in microchip.yaml to reflect this and explicitly add the binding to the SoC's MAINTAINERS entry. Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- Two patches seemed overkill for this, but scream and I will split them. I figured I would take this for 6.1 myself on top of my other changes to microchip.yaml. --- Documentation/devicetree/bindings/riscv/microchip.yaml | 4 ++-- MAINTAINERS | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 37f97ee4fe46..9eaa21769457 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire SoC-based boards maintainers: - - Cyril Jean <Cyril.Jean@xxxxxxxxxxxxx> - - Lewis Hanly <lewis.hanly@xxxxxxxxxxxxx> + - Conor Dooley <conor.dooley@xxxxxxxxxxxxx> + - Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> description: Microchip PolarFire SoC-based boards diff --git a/MAINTAINERS b/MAINTAINERS index cc549debe20c..7d788e064390 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17572,6 +17572,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +F: Documentation/devicetree/bindings/riscv/microchip.yaml F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml -- 2.36.1
