Before initiating the programming sequence, this patch generates a low pulse on FPGA's program_n pin which enables the FPGA's in circuit programming interface. Signed-off-by: Johannes Zink <j.zink@xxxxxxxxxxxxxx> --- drivers/fpga/machxo2-common.c | 15 +++++++++++++++ drivers/fpga/machxo2-common.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/fpga/machxo2-common.c b/drivers/fpga/machxo2-common.c index d93c304cceb9..ccf9a50fc590 100644 --- a/drivers/fpga/machxo2-common.c +++ b/drivers/fpga/machxo2-common.c @@ -167,6 +167,17 @@ static int machxo2_write_init(struct fpga_manager *mgr, return -ENOTSUPP; } + if (priv->fpga_program_n) { + /* set fpga in program mode. The timing is chosen very + * conservatively, since the MachXO2 Family Datasheet + * indicates a low pulse longer than 55ns will be accepted + */ + gpiod_set_value_cansleep(priv->fpga_program_n, 1); + usleep_range(1000, 1500); + gpiod_set_value_cansleep(priv->fpga_program_n, 0); + usleep_range(1000, 1500); + } + priv->get_status(priv, &status); dump_status_reg(priv->dev, status); @@ -331,6 +342,10 @@ int machxo2_common_init(struct machxo2_common_priv *priv, struct device *dev) priv->erase_cmd = cpu_to_be32(erase_cmd); + priv->fpga_program_n = devm_gpiod_get_optional(dev, + "lattice,program", + GPIOD_OUT_LOW); + priv->dev = dev; mgr = devm_fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", diff --git a/drivers/fpga/machxo2-common.h b/drivers/fpga/machxo2-common.h index 1b54154f91b1..0f9f53b48152 100644 --- a/drivers/fpga/machxo2-common.h +++ b/drivers/fpga/machxo2-common.h @@ -32,6 +32,7 @@ struct machxo2_common_priv { int (*get_status)(struct machxo2_common_priv *priv, u32 *status); struct device *dev; __be32 erase_cmd; + struct gpio_desc *fpga_program_n; }; int machxo2_common_init(struct machxo2_common_priv *priv, struct device *dev); -- 2.30.2