Updates binding document for the zynqmp afi config node to handle the
PS_PL Bus-width and resets.
Signed-off-by: Nava kishore Manne <nava.kishore.manne@xxxxxxx>
---
.../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
index f14f7b454f07..9504665cad95 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -59,6 +59,13 @@ properties:
controller.
type: object
+ zynqmp-fpga:
+ $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
+ description: The Zynq UltraScale+ MPSoC Processing System core provides
+ access from PL masters to PS internal peripherals, and memory through
+ AXI FIFO interface(AFI)
+ type: object
+
required:
- compatible
--
2.25.1
