On Fri, 29 Jul 2022 09:30:18 +0900, Chanho Park wrote:
> CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
> Lanes. Similarly, CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1,
> 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also
> supported as a PLL source clock provider.
>
> Changes since v1:
> - Patch 0002 and 0006: Put FYS1 prefix for CLK_MOUT_MMC_PLL as pointed
> by Chanwoo
> - Add Chanwoo and Krzysztof A-B and R-B tags to 0001/0003/0004 and 0005
> patches
>
> [...]
Applied, thanks!
[1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
https://git.kernel.org/krzk/linux/c/153da489e5e7c9aed7e6445b9450d98d5ebd5a5b
[2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
https://git.kernel.org/krzk/linux/c/3c073243c5df0146fef619f7aa5874b2e9d234a3
[3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
https://git.kernel.org/krzk/linux/c/4b6ec8d88623fed87088f141bcce79f67d82f301
[4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
https://git.kernel.org/krzk/linux/c/ac94f66521a5488eccdded4036b0ec039ceb87d5
[5/6] clk: samsung: exynosautov9: add fsys0 clock support
https://git.kernel.org/krzk/linux/c/3477b3c3a9fbb6422874c7f24a35249e1773c687
[6/6] clk: samsung: exynosautov9: add fsys1 clock support
https://git.kernel.org/krzk/linux/c/65522e7d86c986df77bd3106de1ef7712070ee7e
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
