CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 Lanes. Similarly, CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Changes since v1: - Patch 0002 and 0006: Put FYS1 prefix for CLK_MOUT_MMC_PLL as pointed by Chanwoo - Add Chanwoo and Krzysztof A-B and R-B tags to 0001/0003/0004 and 0005 patches Chanho Park (6): dt-bindings: clk: exynosautov9: add fys0 clock definitions dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 arm64: dts: exynosautov9: add fsys0/1 clock DT nodes clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: add fsys1 clock support .../clock/samsung,exynosautov9-clock.yaml | 44 +++ arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++ drivers/clk/samsung/clk-exynosautov9.c | 373 ++++++++++++++++++ .../dt-bindings/clock/samsung,exynosautov9.h | 68 ++++ 4 files changed, 513 insertions(+) -- 2.37.1
