On 8/9/22 1:21 AM, Krzysztof Kozlowski wrote: > On 08/08/2022 18:16, Sean Anderson wrote: >> >>> This entry here is not >>> parsed for any tools and only sometimes people look at it. The questions >>> are directed via entry in maintainers file or via git history, so you >>> can put company email just there. >> >> As I understand it, the email is simply informative. There are literally >> hundreds of examples of mixing a "personal" copyright with a company email. >> It is easy to find if you grep. If you are so opposed to it, then I will >> remove the email and simply use my name. > > No, no problem for me. > >> >>>> >>>>>> + */ >>>>>> + >>>>>> +#ifndef __DT_BINDINGS_CLK_LYNX_10G_H >>>>>> +#define __DT_BINDINGS_CLK_LYNX_10G_H >>>>>> + >>>>>> +#define LYNX10G_CLKS_PER_PLL 2 >>>>>> + >>>>>> +#define LYNX10G_PLLa(a) ((a) * LYNX10G_CLKS_PER_PLL) >>>>>> +#define LYNX10G_PLLa_EX_DLY(a) ((a) * LYNX10G_CLKS_PER_PLL + 1) >>>>> >>>>> These do not look like proper IDs for clocks for bindings. Numbering >>>>> starts from 0 or 1 and any "a" needs to be clearly explained. What do >>>>> you bind here? >>>> >>>> This matches "a" is the index of the PLL. E.g. registers PLL1RSTCTL etc. >>>> This matches the notation used in the reference manual. >>> >>> This is a file for bindings, not for storing register values. There is >>> no single need to store register values (offsets, indexes) as bindings >>> as it is not appropriate. Therefore if you do not use it as an ID, just >>> remove the bindings header. >> >> This *is* just for IDs, as stated in the commit message. The above example >> was only to illustrate that the clock controlled via the PLL1RSTCTL register >> (among others) would have an ID of LYNX10G_PLLa(0). >> >> If you doubt it, review the driver. > > Indeed, thanks. Except the driver, where is the DTS user of these > bindings? It's neither in bindings example, nor in the DTS patches. The primary purpose is to allow using assigned-clocks. The reference manual for the processor may specify that certain PLLs must be used with a certain rate when in some configuration (this is not necessary for the LS1046A or LS1088A, but there are restrictions for e.g. the LS1043A). Using assigned-clock-rates allows specifying which PLL is to be used at which rate (especially if it differs from the bootloader). Of course, the driver could adjust this later, but it will always use the configured PLL rate before reconfiguring anything. --Sean
