Hi, Bo-Chen: On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@xxxxxxxxxxxx> > > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > --- [snip] > +#define MTK_DP_ENC0_P0_3038 (ENC0_OFFSET + 0x38) > +#define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK BIT(11) > +#define VIDEO_SOURCE_SEL_DP_ENC0_P0_SHIFT (BIT(0) | BIT(1) | > BIT(3)) It's not necessary to define a symbol for shift because it's trivial that we understand it's a shift. > + > +#define MTK_DP_ENC0_P0_303C (ENC0_OFFSET + 0x3C) > +#define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0) > +#define SRAM_START_READ_THRD_DP_ENC0_P0_SHIFT 0 Ditto. > +#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8) > +#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_SHIFT BIT(3) Ditto. Regards, CK > + >
