The AC5/AC5X SoC has 4 UART blocks. Add the additional UART1-3 blocks to the base dtsi file. Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx> --- Notes: This applies on top of the series adding the AC5/AC5X SoC which is in Gregory's mvebu/dt64 tree but hasn't made it to Linus's (yet). arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 80b44c7df56a..914fcf9e2c24 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -95,6 +95,36 @@ uart0: serial@12000 { status = "okay"; }; + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x11000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + mdio: mdio@22004 { #address-cells = <1>; #size-cells = <0>; -- 2.37.1