Hi, Bo-Chen: On Wed, 2022-07-27 at 12:50 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@xxxxxxxxxxxx> > > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx> > --- [snip] > + > +#define MTK_DP_ENC0_P0_31D0 (ENC0_OFFSET + 0x1D0) MTK_DP_ENC0_P0_31D0 is uselese, so remove it. > +#define VSC_EXT_CEA_HB0_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define VSC_EXT_CEA_HB1_DP_ENC0_P0_MASK GENMASK(15, 8) > +#define VSC_EXT_CEA_HB1_DP_ENC0_P0_SHIFT BIT(3) > + > +#define MTK_DP_ENC0_P0_31D4 (ENC0_OFFSET + 0x1D4) Ditto. > +#define VSC_EXT_CEA_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define VSC_EXT_CEA_HB2_DP_ENC0_P0_SHIFT 0 > +#define VSC_EXT_CEA_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) > + > +#define MTK_DP_ENC0_P0_31D8 (ENC0_OFFSET + 0x1D8) Ditto. > +#define VSC_EXT_VESA_NUM_DP_ENC0_P0_MASK GENMASK(5, 0) > +#define VSC_EXT_VESA_NUM_DP_ENC0_P0_SHIFT 0 > +#define VSC_EXT_CEA_NUM_DP_ENC0_P0_MASK GENMASK(13, 8) > +#define VSC_EXT_CEA_NUM_DP_ENC0_P0_SHIFT BIT(3) > + > +#define MTK_DP_ENC0_P0_31DC (ENC0_OFFSET + 0x1DC) Ditto. Regards, CK > +#define HDR0_CFG_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define HDR0_CFG_DP_ENC0_P0_SHIFT 0 > +#define MTK_DP_ENC0_P0_31E8 (ENC0_OFFSET + 0x1E8) > +#define MTK_DP_ENC0_P0_31EC (ENC0_OFFSET + 0x1EC) > +#define AUDIO_CH_SRC_SEL_DP_ENC0_P0_MASK BIT(4) > +#define AUDIO_CH_SRC_SEL_DP_ENC0_P0_SHIFT BIT(2) > +#define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) > +#define ISRC1_HB3_DP_ENC0_P0_SHIFT BIT(3) > +
