On Thu, 28 Jul 2022 17:34:11 +0300, Serge Semin wrote:
> Currently both DW PCIe Root Port and End-point DT bindings are defined as
> separate schemas. Carefully looking at them, at the hardware reference
> manuals and seeing there is a generic part of the driver used by the both
> RP and EP drivers we can greatly simplify the DW PCIe controller bindings
> by moving some of the properties into the common DT schema. It concerns
> the PERST GPIO control, number of lanes, number of iATU windows and CDM
> check properties. They will be defined in the snps,dw-pcie-common.yaml
> schema which will be referenced in the DW PCIe Root Port and End-point DT
> bindings in order to evaluate the common for both of these controllers
> properties. The rest of properties like reg{,-names}, clock{s,-names},
> reset{s,-names}, etc will be consolidate there in one of the next commits.
>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/
> by the Rob' request. (@Rob)
> ---
> .../bindings/pci/snps,dw-pcie-common.yaml | 76 +++++++++++++++++++
> .../bindings/pci/snps,dw-pcie-ep.yaml | 31 +-------
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 33 +-------
> 3 files changed, 78 insertions(+), 62 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
