On Mon, Jul 25, 2022 at 3:54 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
> On Mon, Jul 25, 2022 at 11:32 AM Andy Shevchenko
> <andy.shevchenko@xxxxxxxxx> wrote:
> > On Thu, Jul 21, 2022 at 11:32 AM Marcus Folkesson
> > <marcus.folkesson@xxxxxxxxx> wrote:
...
> > Sorry for my absence of understanding, but why?
> > SPI has MOSI, CLK, CS, where the last one is exactly for that. No?
>
> Forgive me if I misunderstand, but if you use CS that
> way, the way that the SPI framework works is to assert
> CS then transfer a few chunks over SPI (MOSI/CLK)
> then de-assert CS.
No, CS here is used exactly for what it is designed for ("tell that
this message is *for me*"). Yes, hardware implementation here is a
latch register. Because otherwise ALL messages are "for me" which is
wrong. Is it wrong interpretation of the hardware and SPI?
> If CS is used for strobe, it is constantly asserted
> during transfer and the sequence will be latched
> out immediately as you write the SPI transfers and
> the data is clocked through the register, making the
> whole train of zeroes and ones flash across the
> output pins before they stabilize after the SPI
> transfer is finished.
I'm not sure I understand the stabilization issue here. It's how SPI
normally works and we have a lot of delays here and there related to
the phase of the CS in comparison to clock and data. We have a lot of
time to stabilize the outputs of the shift register before latching
it. Did I miss anything?
> If you first do the SPI transfer, then strobe after
> finished, this will not happen.
I have hardware, I have tested it and I understand what you mean by
"stabilizing", but finishing transfer _is_ CS toggling for _this_
chip. No?
> Then it should be a separate pin, so this doesn't
> happen, right?
I think no, you don't need it. I.o.w. either I'm missing something
very interesting about both this kind of chips and SPI basics (shame
on me in this case) or...?
--
With Best Regards,
Andy Shevchenko
