On Mon, Jul 25, 2022 at 3:54 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > > On Mon, Jul 25, 2022 at 11:32 AM Andy Shevchenko > <andy.shevchenko@xxxxxxxxx> wrote: > > On Thu, Jul 21, 2022 at 11:32 AM Marcus Folkesson > > <marcus.folkesson@xxxxxxxxx> wrote: > > > > > > 74hc4094 and 75hc4094 works similar to 74x164 but has an additional > > > storage latch associated with each stage for strobing data from the > > > serial input to parallell buffer tri-state output. > > > > parallel > > > > > Add support for an optional strobe pin. > > > > Sorry for my absence of understanding, but why? > > SPI has MOSI, CLK, CS, where the last one is exactly for that. No? > > Forgive me if I misunderstand, but if you use CS that > way, the way that the SPI framework works is to assert > CS then transfer a few chunks over SPI (MOSI/CLK) > then de-assert CS. > > If CS is used for strobe, it is constantly asserted > during transfer and the sequence will be latched > out immediately as you write the SPI transfers and > the data is clocked through the register, making the > whole train of zeroes and ones flash across the > output pins before they stabilize after the SPI > transfer is finished. > > If you first do the SPI transfer, then strobe after > finished, this will not happen. > > Then it should be a separate pin, so this doesn't > happen, right? > > Yours, > Linus Walleij -- With Best Regards, Andy Shevchenko
